
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:22:24 01/30/2011
-- Design Name:   RS232_RX
-- Module Name:   E:/test_PIC/tb_RS232_RX.vhd
-- Project Name:  test_PIC
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RS232_RX
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
   use ieee.std_logic_arith.all;
   use ieee.std_logic_unsigned.all;

ENTITY tb_RS232_RX_vhd IS
END tb_RS232_RX_vhd;

ARCHITECTURE testbench OF tb_RS232_RX_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT RS232_RX
	PORT(
		Clk : IN std_logic;
		Reset : IN std_logic;
		LineRD_in : IN std_logic;          
		Valid_out : OUT std_logic;
		Code_out : OUT std_logic;
		Store_out : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL Clk :  std_logic := '0';
	SIGNAL Reset :  std_logic := '0';
	SIGNAL LineRD_in :  std_logic := '0';

	--Outputs
	SIGNAL Valid_out :  std_logic;
	SIGNAL Code_out :  std_logic;
	SIGNAL Store_out :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: RS232_RX PORT MAP(
		Clk => Clk,
		Reset => Reset,
		LineRD_in => LineRD_in,
		Valid_out => Valid_out,
		Code_out => Code_out,
		Store_out => Store_out
	);

p_clk : PROCESS
  BEGIN
     Clk <= '1', '0' after 25 ns;
     wait for 50 ns;
  END PROCESS;
  
 --LineRD_in<= '0', 
	--			 '1' after 70000 ns,
		--		 '0' after 90000 ns;
--				 '1' after 16000 ns, 
--				 '0' after 79500 ns;
  
  Reset <= '0', '1' after 10 ns;

END testbench;